The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
It is important for contacts to be coupled properly with the contact regions, such as gate and source/drain (S/D) contact regions, of the transistors. However, processing errors may cause expanded contact profiles. As a result, the separation distance between the S/D contacts and the gate is reduced. This may lead to electrical shorts between the S/D contacts and the gate. Furthermore, processing errors may also form expanded conductive lines which may undesirably lead to electrical shorts between the conductive lines above and the gate below. In cases where there are more than one type of devices formed on the same substrate, contact profile uniformity is also difficult to control due to the different heights of these different devices. These phenomena adversely render the IC malfunction.
From the foregoing discussion, it is desirable to provide a device which is devoid of the above-mentioned problem, thus increasing the reliability of the IC. It is also desirable to provide a simplified process for forming a device with increased reliability.